The element area of a semiconductor integrated circuit is gradually reduced for each generation with an increase in the integration density and miniaturization of the semiconductor integrated circuit as is represented by a DRAM. In a DRAM in which each memory cell is formed of one transistor and one capacitor, a reduction in the element area causes a reduction in the area of the capacitor for storing information so that the information storing function may be deteriorated.
Therefore, various devices are made to securely attain a sufficiently large capacitance of the capacitor so as to prevent the information storing function from being deteriorated by the high integration density and miniaturization in the DRAM. One of the devices is to form the capacitor in the 3-dimensional form, that is, use a trench capacitor or stacked capacitor.
As the trench capacitor, a structure called a substrate plate type is mainly used for the DRAM of 64 Mbit or more. The important point in the memory cell using the substrate plate type trench capacitor is the structure of a connecting portion between the storage node electrode (the electrode buried in the trench) of the capacitor and the source/drain diffusion layer of the transistor.
As one of the structures of the connecting portions, a buried strap structure is known. FIG. 8 is a cross sectional view showing a DRAM memory cell having the buried strap structure. In FIG. 8, a reference numeral 80 denotes a single crystal silicon substrate, 81 a plate electrode, 82 a capacitor insulating film, 83 a collar oxide film, 84.sub.1, 84.sub.2 storage node electrodes, 85 a buried strap (polysilicon film), 86, 87 source/drain diffusion layers, 88 a gate insulating film, 89 a gate electrode and 90 an element isolation insulating film for STI (Shallow Trench isolation).
In this type of memory cell, the electrical connection between the source/drain diffusion layer 86 and the storage node electrode 86 is attained by use of the buried trap 85. The buried strap 85 has an advantage that it can be formed in a self-alignment manner without using the photolithography process using a mask. Further, it also has an advantage that the area is not increased by formation of the buried strap 85.
In the above type of memory cell, the following problem on the process occurred.
In a case where an oxide film such as a natural oxide film is not formed on the interface between the buried strap 85 and the single crystal silicon substrate 80 in an area used as the source/drain diffusion layer 86, that is, when the interface is extremely clean, the epitaxial growth occurs from the side surface of the trench towards the buried strap 85 in the post process of high temperature, for example, in the formation process of the element isolation insulating film 90.
More specifically, as shown in FIG. 9, a wedge-shaped epitaxial region 91 is formed in the buried strap 85. As a result, local mechanical stress occurs and transfer 92 occurs in the substrate. The transfer 92 causes an increase in the junction leak current, thereby deteriorating the data holding characteristic of the DRAM.